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M34C02-W M34C02-L M34C02-R
2 Kbit Serial IC Bus EEPROM for DIMM serial presence detect
Feature summary

Software Data Protection for lower 128 Bytes Two Wire I2C Serial Interface 400kHz Transfer Rates Single Supply Voltage: - 2.5 to 5.5V for M34C02-W - 2.2 to 5.5V for M34C02-L - 1.8 to 5.5V for M34C02-R Byte and Page Write (up to 16 bytes) Random and Sequential Read modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 million Write cycles More than 40 Year Data Retention Packages - ECOPACK(R) (RoHS compliant) UFDFPN8 (MB) 2x3mm (MLP)

TSSOP8 (DW) 169 mil width
April 2006
Rev 9
1/31
www.st.com 1
Contents
M34C02-W, M34C02-L, M34C02-R
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.1 2.5.2 2.5.3 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the Software Write-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.1 3.7.2 3.7.3 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16
3.8
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8.1 3.8.2 3.8.3 3.8.4 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Use within a DRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Programming the M34C02-W, M34C02-L and M34C02-R . . . . . . . . . . . . 19
5
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/31
M34C02-W, M34C02-L, M34C02-R
Contents
6 7 8 9 10
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of tables
M34C02-W, M34C02-L, M34C02-R
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DRAM DIMM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating Conditions (M34C02-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating Conditions (M34C02-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating Conditions (M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Characteristics (M34C02-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Characteristics (M34C02-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC Characteristics (M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC Characteristics M34C02-W, M34C02-L, M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 28 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/31
M34C02-W, M34C02-L, M34C02-R
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TSSOP and MLP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Enable input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum RP value versus bus parasitic capacitance (C) for an IC Bus . . . . . . . . . . . . . . 9 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Setting the Write Protection Register (WC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Serial presence detect block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TSSOP8 - 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 28
5/31
Summary description
M34C02-W, M34C02-L, M34C02-R
1
Summary description
The M34C02-W, M34C02-L and M34C02-R are 2Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. This bottom half of the memory area can be write-protected using a specially designed software write protection mechanism. By sending the device a specific sequence, the first 128 Bytes of the memory become permanently write protected. Care must be taken when using this sequence as its effect cannot be reversed. In addition, the device allows the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC). These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits. In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second Device Type Identifier Code (0110) to access the Protection Register. These codes are used together with three chip enable inputs (E2, E1, E0) so that up to eight 2Kbit devices may be attached to the IC bus and selected individually. The device behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.
6/31
M34C02-W, M34C02-L, M34C02-R Figure 1. Logic diagram
VCC
Summary description
3 E0-E2 SCL WC M34C02-W M34C02-L M34C02-R SDA
VSS
AI01931b
Figure 2.
TSSOP and MLP connections (top view)
M34C02-W M34C02-L M34C02-R E0 E1 E2 VSS 1 2 3 4 8 7 6 5 VCC WC SCL SDA
AI01932d
1. See Section 8: Package mechanical for package dimensions, and how to identify pin-1.
Table 1.
E0, E1, E2 SDA SCL WC VCC VSS
Signal names
Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
7/31
Signal description
M34C02-W, M34C02-L, M34C02-R
2
2.1
Signal description
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
2.2
Serial Data (SDA)
This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to VCC or VSS to establish the Device Select Code. Figure 3. Chip Enable input connection
VCC VCC
M34C02-W M34C02-L M34C02-R Ei
M34C02-W M34C02-L M34C02-R Ei
VSS
VSS
Ai12819
2.4
Write Control (WC)
This input signal is provided for protecting the contents of the whole memory from inadvertent write operations. Write Control (WC) is used to enable (when driven Low) or disable (when driven High) write instructions to the entire memory area or to the Protection Register. When Write Control (WC) is tied Low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register.
8/31
M34C02-W, M34C02-L, M34C02-R
Signal description
2.5
2.5.1
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 6, Table 7 and Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
2.5.2
Internal device reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any instruction until VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 6, Table 7 and Table 8). When VCC has passed the POR threshold, the device is reset and in the Standby Power mode.
2.5.3
Power-down
At Power-down (where VCC decreases continuously), as soon as VCC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected and in Standby Power mode (that is there should be no internal Write cycle in progress). Figure 4.
20 16 RP SDA MASTER fc = 100kHz fc = 400kHz SCL C RP 12 8 4 0 10 100 C (pF)
AI01665b
Maximum RP value versus bus parasitic capacitance (C) for an IC Bus
VCC
Maximum RP value (k)
C 1000
9/31
Signal description Figure 5. I2C bus protocol
M34C02-W, M34C02-L, M34C02-R
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
Table 2.
Device Select Code
Device Type Identifier(1) b7 b6 0 1 b5 1 1 b4 0 0 Chip Enable Address(2) b3 E2 E2 b2 E1 E1 b1 E0 E0 RW b0 RW RW
Memory Area Select Code (two arrays) Protection Register Select Code
1 0
1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device.
10/31
M34C02-W, M34C02-L, M34C02-R
Device operation
3
Device operation
The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The memory device is always a slave in all communication.
3.1
Start Condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop Condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle.
3.3
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.
3.4
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.
11/31
Device operation
M34C02-W, M34C02-L, M34C02-R
3.5
Memory Addressing
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b; to address the Protection Register, it is 0110b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode. Table 3. Operating Modes
Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write
1. X = VIH or VIL.
RW bit 1 0 1 1 0 0
WC(1) X X
Bytes 1 1
Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1
X X VIL VIL 1 1 16
Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0
Figure 6.
Setting the Write Protection Register (WC = 0)
START
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY ACK ACK ACK CONTROL BYTE WORD ADDRESS
DATA
VALUE VALUE (DON'T CARE) (DON'T CARE)
AI01935B
12/31
STOP
M34C02-W, M34C02-L, M34C02-R
Device operation
3.6
Setting the Software Write-Protection
The M34C02-W has a hardware write-protection feature, using the Write Control (WC) signal. This signal can be driven High or Low, and must be held constant for the whole instruction sequence. When Write Control (WC) is held Low, the whole memory array (addresses 00h to FFh) is write protected. When Write Control (WC) is held High, the write protection of the memory array is dependent on whether software write-protection has been set. Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh) to be permanently write protected irrespective of subsequent states of the Write Control (WC) signal. The write protection feature is activated by writing once to the Protection Register. The Protection Register is accessed with the device select code set to 0110b (as shown in Table 2), and the E2, E1 and E0 bits set according to the states being applied on the E2, E1 and E0 signals. As for any other write command, Write Control (WC) needs to be held Low. Address and data bytes must be sent with this command, but their values are all ignored, and are treated as Don't Care. Once the Protection Register has been written, the write protection of the first 128 Bytes of the memory is enabled, and it is not possible to unprotect these 128 Bytes, even if the device is powered off and on, and regardless the state of Write Control (WC). When the Protection Register has been written, the M34C02-W no longer responds to the device type identifier 0110b in either read or write mode. Figure 7. Result of setting the write protection
FFh Standard Array Memory Area Standard Array 00h Default EEPROM memory area state before write access to the Protect Register 80h 7Fh Standard Array Write Protected Array
FFh
80h 7Fh
00h
State of the EEPROM memory area after write access to the Protect Register
AI01936C
13/31
Device operation
M34C02-W, M34C02-L, M34C02-R
3.7
Write Operations
Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests.
3.7.1
Byte Write
After the Device Select Code and the address byte, the bus master sends one data byte. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the location is not modified. If, instead, the addressed location is not Writeprotected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8.
3.7.2
Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.
14/31
M34C02-W, M34C02-L, M34C02-R Figure 8. Write mode sequences in a non write-protected area
ACK BYTE WRITE START DEV SEL R/W ACK PAGE WRITE START DEV SEL R/W ACK DATA IN N STOP ACK ACK DATA IN 1 ACK DATA IN ACK
Device operation
BYTE ADDR
ACK DATA IN 2
BYTE ADDR
STOP
AI01941
15/31
Device operation
M34C02-W, M34C02-L, M34C02-R
3.7.3
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 14 and Table 16, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is:

Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Write cycle polling flowchart using ACK
WRITE Cycle in Progress
Figure 9.
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
16/31
M34C02-W, M34C02-L, M34C02-R
Device operation
3.8
Read Operations
Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read.
3.8.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
3.8.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte.
3.8.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h.
3.8.4
Acknowledge in Read Mode
For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode.
17/31
Device operation Figure 10. Read mode sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W
M34C02-W, M34C02-L, M34C02-R
NO ACK DATA OUT STOP ACK DEV SEL * START R/W
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK
NO ACK DATA OUT STOP NO ACK ACK
AI01942
BYTE ADDR
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
18/31
M34C02-W, M34C02-L, M34C02-R
Use within a DRAM DIMM
4
Use within a DRAM DIMM
In the application, the M34C02-W, M34C02-L and M34C02-R are soldered directly in the printed circuit module. The 3 Chip Enable inputs (pins 1, 2 and 3) are wired at VCC or VSS through the DIMM socket (see Table 4). The pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the mother-board (as shown in Figure 11). The Write Control (WC) of the M34C02-W, M34C02-L and M34C02-R can be left unconnected. However, connecting it to VSS is recommended, to maintain full read and write access.
4.1
Programming the M34C02-W, M34C02-L and M34C02-R
When the device is delivered, full read and write access is given to the whole memory array. It is recommended that the first step is to use the test equipment to write the module information (such as its access speed, its size, its organization) to the first half of the memory, starting from the first memory location. When the data has been validated, the test equipment can send a Write command to the Protection Register, using the device select code '01100000b' followed by an address and data byte (made up of Don't Care values) as shown in Figure 6. The first 128 bytes of the memory area are then write-protected, and the M34C02-W, M34C02-L and M34C02-R will no longer respond to the specific device select code '0110000xb'. It is not possible to reverse this sequence. Table 4. DRAM DIMM Connections
DIMM Position 0 1 2 3 4 5 6 7 E2 VSS VSS VSS VSS VCC VCC VCC VCC E1 VSS VSS VCC VCC VSS VSS VCC VCC E0 VSS VCC VSS VCC VSS VCC VSS VCC
19/31
Initial delivery state
M34C02-W, M34C02-L, M34C02-R
5
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each Byte contains FFh). Figure 11. Serial presence detect block diagram
DIMM Position 7 E2 E1 VCC DIMM Position 6 E2 E1 E0 SCL SDA E0 SCL SDA
R = 4.7k
VCC DIMM Position 5 E2 E1
VSS
E0
SCL SDA
VCC VSS VCC DIMM Position 4 E2 VCC DIMM Position 3 E2 VSS DIMM Position 2 E2 E1 E0 SCL SDA E1 E0 VCC SCL SDA E1 E0 VSS SCL SDA
VSS VCC VSS DIMM Position 1 E2 VSS DIMM Position 0 E2 E1 E0 SCL SDA E1 E0 VCC SCL SDA
VSS SCL line SDA line
AI01937
From the motherboard I2C master controller
1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices. 2. Common clock and common data are shared across all the devices. 3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 k) because these lines are open drain when used as outputs.
20/31
M34C02-W, M34C02-L, M34C02-R
Maximum rating
6
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5.
Symbol TA TSTG TLEAD VIO VCC VESD
Absolute maximum ratings
Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Input or Output Voltage Supply Voltage Electrostatic Discharge Voltage (Human Body model)(2) Soldering(1) Min. -40 -65 See -0.50 -0.50 -4000
(1)
Max. 90 150
Unit C C C
6.5 6.5 4000
V V V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
21/31
DC and AC parameters
M34C02-W, M34C02-L, M34C02-R
7
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 6.
Symbol VCC TA Supply Voltage Ambient Operating Temperature
Operating Conditions (M34C02-W)
Parameter Min. 2.5 -40 Max. 5.5 85 Unit V C
Table 7.
Symbol VCC TA
Operating Conditions (M34C02-L)
Parameter Supply Voltage Ambient Operating Temperature Min. 2.2 -40 Max. 5.5 85 Unit V C
Table 8.
Symbol VCC TA
Operating Conditions (M34C02-R)
Parameter Supply Voltage Ambient Operating Temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 9.
Symbol CL
AC Measurement Conditions
Parameter Load Capacitance Input Rise and Fall Times Input Levels Input and Output Timing Reference Levels Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 12. AC Measurement I/O Waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
22/31
M34C02-W, M34C02-L, M34C02-R Table 10.
Symbol CIN CIN ZWCL ZWCH tNS
DC and AC parameters
Input Parameters
Parameter(1),(2) Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Pulse width ignored (Input Filter on SCL and SDA) VIN < 0.3 V VIN > 0.7VCC Single glitch 15 500 100 Test Condition Min. Max. 8 6 70 Unit pF pF k k ns
1. TA = 25C, f = 400kHz 2. Sampled only, not 100% tested.
Table 11.
Symbol
DC Characteristics (M34C02-W)
Parameter Input Leakage Current (SCL, SDA, E0, E1,and E2) Output Leakage Current Test Condition (in addition to those in Table 6) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC=5V, fc=400kHz (rise/fall time < 30ns) Min. Max. Unit
ILI ILO
2 2 2 1 1 -0.45 0.7VCC 0.3VCC VCC+1 0.4
A A mA mA A V V V
ICC
Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) Stand-by Supply Current Input Low Voltage (1) Input High Voltage
(1)
ICC1 VIL VIH VOL
VIN = VSS or VCC, for 2.5V < VCC = < 5.5V
Output Low Voltage
IOL = 2.1mA when VCC = 2.5V or IOL = 3mA when VCC = 5.5V
1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.
23/31
DC and AC parameters Table 12.
Symbol ILI ILO
M34C02-W, M34C02-L, M34C02-R DC Characteristics (M34C02-L)
Parameter Test Condition (in addition to those in Table 7) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC =5V, fc=400kHz (rise/fall time < 30ns) Min. Max. 2 2 2 1 1 1 0.5 -0.3 -0.3 0.3VCC 0.5 Unit A A mA mA mA A A V V V V V
Input Leakage Current (SCL, SDA) Output Leakage Current
ICC
Supply Current
VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VCC =2.2V, fc=400kHz (rise/fall time < 30ns)
ICC1
Stand-by Supply Current Input Low Voltage (E2, E1, E0, SCL, SDA) Input Low Voltage (WC)
VIN = VSS or VCC , VCC = 5 V VIN = VSS or VCC , 2.2V VCC < 2.5V
VIL
VIH VOL
Input High Voltage (E2, E1, E0, SCL, SDA, WC) Output Low Voltage IOL = 3mA, VCC = 5V IOL = 2.1mA, 2.2V VCC < 2.5V
0.7VCC VCC+1 0.4 0.4
24/31
M34C02-W, M34C02-L, M34C02-R Table 13.
Symbol ILI ILO
DC and AC parameters
DC Characteristics (M34C02-R)
Parameter Test Condition (in addition to those in Table 8) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC =5V, fc=400kHz (rise/fall time < 30ns) Min. Max. 2 2 2 1 1 1 0.5 - 0.3 - 0.3 0.7VCC IOL = 3mA, VCC = 5V IOL = 2.1mA, 2.2V VCC < 2.5V IOL = 0.15mA, VCC = 1.8V 0.3VCC 0.25VCC VCC+1 0.4 0.4 0.2 Unit A A mA mA mA A A V V V V V V
Input Leakage Current (SCL, SDA, E0, E1 and E2) Output Leakage Current
ICC
Supply Current
VCC =2.5V, fc=400kHz (rise/fall time < 30ns) VCC =1.8V, fc=400kHz (rise/fall time < 30ns)
ICC1 VIL VIH VOL
Stand-by Supply Current Input Low Voltage(1) Input High Voltage (1)
VIN = VSS or VCC , VCC = 5V VIN = VSS or VCC , 1.8V VCC < 2.5V 2.5V VCC 5.5V 1.8V VCC < 2.5V
Output Low Voltage
1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1k.
Table 14.
AC Characteristics M34C02-W, M34C02-L, M34C02-R)
Test conditions specified in Table 9 and Table 6 or Table 7
Symbol fC tCHCL tCLCH tDL1DL2
(1)
Alt. fSCL tHIGH tLOW tF Clock Frequency
Parameter
Min.
Max. 400
Unit kHz ns ns
Clock Pulse Width High Clock Pulse Width Low SDA Fall Time
600 1300 20 100 0 200 200 600 600 600 1300 10 900 300
ns ns ns ns ns ns ns ns ns ms
tDXCX tCLDX tCLQX tCLQV(2) tCHDX(3) tDLCL tCHDH tDHDL tW
tSU:DAT Data In Set Up Time tHD:DAT Data In Hold Time tDH tAA Data Out Hold Time Clock Low to Next Data Valid (Access Time)
tSU:STA Start Condition Set Up Time tHD:STA Start Condition Hold Time tSU:STO Stop Condition Set Up Time tBUF tWR Time between Stop Condition and Next Start Condition Write Time
1. Sampled only, not 100% tested. 2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. For a reSTART condition, or following a Write cycle.
25/31
DC and AC parameters Figure 13. AC Waveforms
tCHCL tCLCH
M34C02-W, M34C02-L, M34C02-R
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid
AI00795C
tCLQX
26/31
M34C02-W, M34C02-L, M34C02-R
Package mechanical
8
Package mechanical
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 15.
UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Mechanical Data
millimeters inches Max. 0.60 0.05 0.30 0.010 0.079 1.55 1.65 0.05 3.00 0.15 0.50 0.45 - 0.40 0.25 - 0.50 0.15 0.30 8 0.012 8 0.020 0.018 0.118 0.006 - 0.016 0.010 - 0.020 0.006 0.061 0.065 0.002 Typ. 0.022 Min. 0.020 0.000 0.008 Max. 0.024 0.002 0.012
Symbol Typ. A A1 b D D2 ddd E E2 e L L1 L3 N 0.25 2.00 0.55 Min. 0.50 0.00 0.20
27/31
Package mechanical
M34C02-W, M34C02-L, M34C02-R
Figure 15. TSSOP8 - 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 16.
Symbol
TSSOP8 - 8 lead Thin Shrink Small Outline, package mechanical data
millimeters Typ. Min. Max. 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. inches Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1
28/31
M34C02-W, M34C02-L, M34C02-R
Part numbering
9
Part numbering
Table 17.
Example: Device Type M34 = ASSP I2C serial access EEPROM Device Function 02 = 2 Kbit (256 x 8) Operating Voltage W = VCC = 2.5 to 5.5V (400kHz) L = VCC = 2.2 to 5.5V (400kHz) R = VCC = 1.8 to 5.5V (400kHz) Package MB = UDFDFPN8 (MLP8) DW = TSSOP8 (169 mil width) Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 1 = Temperature range 0 to 70 C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology P or G = ECOPACK(R) (RoHS compliant)
Ordering information scheme
M34C02-W - W MB 6 T P
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
29/31
Revision history
M34C02-W, M34C02-L, M34C02-R
10
Revision history
Table 18.
Date
Document revision history
Revision Description of Revision Adjustments to the formatting. 0 to 70C temperature range removed from DC and AC tables. No change to description of device, or parameters New definition of lead soldering temperature absolute rating for certain packages -R voltage range added TSSOP8 (3x3mm body size) package (MSOP8) added VFDFPN8 package (MLP8) added Document reformatted. -F voltage range added. Table of Contents added. MLP package changed. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified Typos corrected in Ordering Information example Device Grade clarified. Product List summary table added SO8 package removed. M34C02-R operating frequency upgraded to 400 kHz. Modified Section 1.1: Device Internal Reset, Figure 4: Maximum RP value versus bus parasitic capacitance (C) for an IC Bus, Table 10: Input Parameters, ICC1 values in Table 11: DC Characteristics (M34C02-W), Table 13: DC Characteristics (M34C02-R), Table 15: DC Characteristics (M34C02-W-F) and moved M34C02-R to Table 14: AC Characteristics M34C02-W, M34C02-L, M34C02-R). Added Figure 3: Chip Enable input connection. Added EcoPack(R) and Ambient Operating Temperature information. BN and DS (PDIP and TSSOP8) packages removed.. M34C02-F part number removed. Test Conditions modified for ICC1 and VOL in Table 11: DC Characteristics (M34C02-W). Device Internal Reset removed and replaced by Section 2.5: Supply voltage (VCC). Blank option removed below Plating Technology in Table 17.
27-Dec-1999
2.0
07-Dec-2000 13-Mar-2001 18-Jul-2002 22-May-2002 21-Jul-2003
2.1 2.2 2.3 2.4 3.0
17-Mar-2004
4.0
14-Apr-2004 26-Aug-2004 30-Nov-2004
5.0 6.0 7.0
14-Oct-2005
8.0
11-Apr-2006
9
30/31
M34C02-W, M34C02-L, M34C02-R
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